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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the technical changes made to the document.
Scope: Applicable updates to the TMS320C5000 device family, specifically relating to the device (Silicon
Revisions 2.0) which is now in the production data (PD) stage of development have been incorporated.
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Global
?
Added notes to clarify that CV DDRTC must always be powered by an external power supply and
none of the on-chip LDOs can power CV DDRTC .
Section 2
Table 2-1 , Characteristics of the C5515 Processor :
Device Overview
?
?
Deleted Power Characterization
Updated addresses for MMC/SD0 and MMC/SD1 in Table 2-4 , Peripheral I/O-Space Control
Registers .
Section 2.5
Table 2-7 , RESET, Interrupts, and JTAG Terminal Functions :
Terminal Functions
?
Deleted duplicate note on board design guidelines.
Table 2-8 , External Memory Interface (EMIF) Terminal Functions :
?
Changed note for 16-bit asynchronous memory to connect EM_A[20:0] to memory address pins
[21:1].
Table 2-13 , USB2.0 Terminal Functions
?
Added power-on information for USB_VBUS, USB_V DDA3P3 , USB_V DDA1P3 , and USB_V DD1P3 .
Table 2-20 , Reserved and No Connects Terminal Functions :
?
Updated RSV16 description to tie directly to V SS .
Section 3
Device Configuration
?
?
Added note stating Device ID registers are reserved.
Updated reset value for WU_DOUT from 0 to 1.
Section 3.4 , Boot Sequence :
?
?
?
Added steps to set register configuration and copy boot image sections (steps 15 and 16).
Changed Figure 3-2 , Bootloader Software Architecture .
Added reset default to pin multiplexing tables.
Section 4
Section 4.3
Device Operating
Conditions
Section 5.3
Power Supplies
?
?
?
Added note for core (CV DD ) supply power (P).
Updated ESD Stress Voltage value for HBM to > 1000 V and CDM to > 250 V.
Updated Section 5.3.1 , Power-Supply Sequencing .
Section 5.5.1
Table 5-3 , PLL Clock Frequency Ranges :
PLL Device-Specific
Information
?
Updated maximum value for PLL_LOCKTIME.
Section 5.8.2
Table 5-8 , Timing Requirements for Wake-Up From IDLE :
Wake-Up From IDLE
Electrical Data/Timing
?
Changed minimum value to 30.5 μs from 10 ns.
Table 5-9 , Switching Characteristics Over Recommended Operating Conditions For Wake-Up From
IDLE :
?
?
Changed parameter description to, "Delay time, WAKEUP pulse complete to CPU active."
Moved 2 to WAKEUP pulse complete from wake-up event high in Figure 5-14 , Wake-Up From
IDLE Timings .
Section 5.9
Global:
External Memory
Interface (EMIF)
Section 5.11
Real-Time Clock (RTC)
?
?
?
Updated device limitations on EM_SDCLK when DV DDEMIF = 1.8 V and 1.3 V.
Added notes to timing and switching tables.
Added to wake-up sequence in Section 5.11.1 , RTC Only Mode .
Section 6
Device and
Documentation Support
Moved documentation support to Section 7 from Section 3.6 and 3.7.
6
Contents
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